Custom Fpga Cryptographic Blocks for Reconfigurable Embedded Nios Processor

This paper introduces two custom blocks for Nios reconfigurable embedded processor implemented on Altera Field Programmable Gate Arrays (FPGAs). When operations like modular multiplication and modular exponentiation of long integers or other complex algebraic functions are performed on a general-purpose processor they usually consume a lot of processor resources and execution times are not satisfactory. A solution of this problem lies in development of custom coprocessors. The algebraic coprocessor for Montgomery Multiplication (MM) makes possible a fast execution of modular multiplication with large numbers that can be used in several public key cryptographic algorithms. A True Random Number Generator (TRNG) enhances an application of the Nios processor in cryptographic protocols. Until now only few implementations of TRNG on FPGA have been presented in literature. We describe a custom TRNG implementation based on a recently proposed method that reliably extracts intrinsic randomness from low-jitter clock signals synthesized by on-chip FPGA analog PLLs. Both peripheral blocks are connected to the Nios processor through Altera Avalon bus that directly supports scalable connection and different sources of the clock signal. In this way we can optimally use the resources of Altera FPGAs and implement designs customisable with regard to available area resources and desired level of security or timing constraints. Proposed solutions significantly improve security and computational power of System on a Chip (SoC) embedded cryptographic applications based on the Nios processor.